The present invention relates to equalizer circuits for data signals, and in particular, to decision feedback equalizer circuits capable of processing multiple data rates.
As digital communication systems continue to be developed with ever increasing data rates, challenges grow for maintaining signal integrity for higher serial data rates. To meet the demands on signal integrity, systems beyond currently existing linear equalizers are needed. One such system is a decision feedback equalizer (DFE) that provides compensation for channel imperfections and bandwidth limitations, crosstalk and low signal-to-noise ratio (SNR). However, current DFE systems fail to provide predictable feedback at the input summation node, and most are capable of working at only a signal data rate and have limited jitter tolerance.
Referring to FIG. 1, as is well known, a typical communications channel will have serial data 11 having a high data rate (e.g., 12 gigabits per second) which is transmitted by a transmitter 12 as a high frequency data signal 13 for conveyance by a communications medium 14 (e.g., coaxial or fiber optic cable) for reception by a linear equalizer 16. The equalized signal 17 is then further compensated by a DFE 18 to provide data 19 for further downstream processing (not shown). However, problems can develop due to discontinuities 15 in the communications path, as well as crosstalk 21 from an adjacent channel 20, both of which introduce further undesirable non-linear signal effects.
A DFE 18 is difficult to implement for reliable operation at high data rates. For example, at a data rate of 10 gigabits per second, a bit width, or unit interval (UI), is 100 picoseconds. For good SNR and bit error rate (BER), this results in an optimal sampling point, which is at the center of the data eye, with only 50 picoseconds available to feed the data back to the input summation node. Further difficulties arise with changes in the data rate and signal jitter.
Referring to FIG. 2, one conventional solution is a DFE 30a which is capable of operating reliably at only one data rate. In accordance with well-known techniques, the incoming data signal 17 is summed in the input summation node 32 with one or more feedback signals 41. The resulting combined, or summed, signal 33 is successively re-timed by multiple latch circuits 34, 36 clocked by the recovered data clock 31. The final latched signal 37 is delayed with delay circuitry 38 having a fixed delay to provide the equalized data 39, which is also fed back via one or more DFE feedback taps 40 (discussed in more detail below). It is the fixed delay of this output delayed circuitry 38 that determines the data rate for which such circuitry 30a is suitable.
Referring to FIG. 3, an alternative DFE 30b uses delay circuitry 38a with a variable delay. However, this variable delay must be controllable so as to be reset for various data rates. Such variable delay also requires sufficient resolution, or granularity, in delay line settings to meet system SNR and BER requirements. Further, the data rate must be known ahead of time, or must be capable of being sensed prior. Such variability can also be problematic in terms of its compatibility with DFE adaptation algorithms, and also increases adaptation timing.
Referring to FIG. 4, an alternative conventional DFE 30c uses no additional delay in the output, but instead introduces delay to the clock signal 31 with a delay circuitry 42 in the clock signal path. Such delay can be fixed or variable, and provides a delayed clock signal 43 for the data latches 34, 36. However, in addition to the problems associated with the DFE 30b of FIG. 3, this DFE 30c also relies on interpolation of two clock phases to provide proper timing for the feedback signal 41.